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Results: 1614

#	Item
101	Energy Efficient Watchpoint Systems MAD WorkshopVasileios Karakostas, Sasa Tomic, Osman Unsal, Mario Nemirovsky, Adrian Cristal Barcelona Supercomputing Center Add to Reading List Source URL: www.mad-workshop.de Language: English - Date: 2016-03-22 12:43:37 Computer memory Cache Computer architecture CPU cache Central processing unit Breakpoint
102	Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering, Add to Reading List Source URL: www.dcs.warwick.ac.uk Language: English - Date: 2014-11-13 12:51:32 Cache Central processing unit Computer memory Computer architecture Parallel computing CPU cache Locality of reference Benchmark Microarchitecture Instruction set Instruction-level parallelism Draft:Cache memory
103	Appears in the Proceedings of the 34 Annual Workshop on Workload Characterization Add to Reading List Source URL: akkartik.name Language: English - Date: 2003-01-10 16:49:02 Computational linguistics Central processing unit Computer memory Computer accessibility Speech recognition CMU Sphinx CPU cache Sphinx Translation lookaside buffer Hidden Markov model Cache Speech synthesis
104	Auto-tuning the 27-point Stencil for Multicore Kaushik Datta2 , Samuel Williams1 , Vasily Volkov2 , Jonathan Carter1 , Leonid Oliker1 , John Shalf1 , and Katherine Yelick1 1 CRD/NERSC, Lawrence Berkeley National Laborat Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:44:43 Compiler optimizations Loop nest optimization Stencil code Roofline model Program optimization Stencil CPU cache Common subexpression elimination Scalable locality
105	Network Options Table Options Use the following onstat options to monitor shared memory and network connection services. Add to Reading List Source URL: www.iiug.org Language: English - Date: 2011-06-16 23:04:57 Concurrent computing Central processing unit Parallel computing Computer memory Thread Monitor CPU cache Synchronization Load Shared memory Session GNU Core Utilities
106	Predicting Memory-Access Cost Based on Data-Access Patterns Surendra Byna Xian-He Sun Illinois Institute of Technology {renbyna, sun}@iit.edu Abstract Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2016-08-16 11:52:12 Cache Computer memory Computer architecture Central processing unit Virtual memory CPU cache Locality of reference Loop interchange Memory hierarchy Loop nest optimization Thrashing Page table
107	Mars: A 64-core ARMv8 Processor Charles Zhang Phytium Technology Co., Ltd Statements The following slides are presented to introduce the Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-24 20:58:27 CPU cache Cache Central processing unit Computer memory Xiaomi
108	Runtime Register Allocation Kemal Ebcio˘glu and Vivek Sarkar IBM T.J. Watson Research Center P.O. Box 704 Yorktown Heights, NY 10598, USA {kemal,vsarkar}@us.ibm.com Add to Reading List Source URL: akkartik.name Language: English - Date: 2006-03-07 01:56:23 Central processing unit Computer architecture NCR Corporation Processor register CPU cache
109	HexPADS: a platform to detect “stealth” attacks Mathias Payer Purdue University Abstract. Current systems are under constant attack from many different sources. Both local and remote attackers try to escalate their p Add to Reading List Source URL: hexhive.github.io Language: English - Date: 2016-06-13 11:08:40 Computer memory Computer architecture Central processing unit Cache CPU cache Parallel computing Row hammer Dynamic random-access memory Shared memory Microarchitecture Draft:Cache memory Cold boot attack

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